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3.1.7
Axis Configuration Register (AXISCFG)
The axis configuration register is a read/write register which contain axis specific configuration information. This register can
be written during initialization, but is locked once the ENDINIT bit is set. This registers is included in the writable register CRC
check. Refer to Section 3.2.2 for details.
Table 10. Axis Configuration Registers
Location
Bit
Address
$0C
Register
AXISCFG
7
ST
6
Reserved
5
Reserved
4
Reserved
3
LPF[3]
2
LPF[2]
1
LPF[1]
0
LPF[0]
Reset Value
0
0
0
0
0
0
0
0
3.1.7.1 Self Test Control (ST)
The ST bit enables and disables the self test circuitry. Self test circuitry is enabled if a logic ‘1’ is written to ST and the ENDINIT
bit has not been set. Enabling the self test circuitry results in a positive acceleration value. Self test deflection values are specified
in Section 2.4 . ST is always cleared following internal reset.
When the self test circuitry is active, the offset cancellation block and the offset monitor status are suspended, and the status
bits in the Acceleration Data Request Response will indicate “Self Test Active”. Reference Section 3.8.4 and Section 4.2 for de-
tails. When the self test circuitry is disabled by clearing the ST bit, the offset monitor remains disabled until the time t ST_OMB spec-
ified in Section 2.5 expires. However, the status bits in the Acceleration Data Request Response will immediately indicate that
self test is deactivated.
When ENDINIT is set, self test is disabled. This can only be changed by a reset. A Register Write will not modify the ST bit
and the response to a Register Read or Write will include the last successful written values for these bits.
3.1.7.2 Reserved Bits (Reserved)
Bits 6 through 4 of the AXISCFG register are reserved. A write to the reserved bits must always be logic ‘0’ for normal device
operation and performance.
3.1.7.3 Low-Pass Filter Selection Bits (LPF[3:0])
The Low Pass Filter selection bit selects a low-pass filter as shown in Table 11 . Refer to Section 3.8.3 for details regarding
filter configurations.
Table 11. Low Pass Filter Selection Bits
LPF[3]
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
LPF[2]
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
LPF[1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
LPF[0]
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Low Pass Filter Selected
100 Hz, 4-pole
300 Hz, 4-pole
400 Hz, 4-pole
800 Hz, 4-pole
1000 Hz, 4-pole
400 Hz, 3-pole
Reserved
Reserved
50 Hz, 4-pole
150 Hz, 4-pole
200 Hz, 4-pole
400 Hz, 4-pole
500 Hz, 4-pole
200 Hz, 3-pole
Reserved
Reserved
Nominal Sample Rate ( μ s)
8
8
8
8
8
8
Reserved
Reserved
16
16
16
16
16
16
Reserved
Reserved
Note: Filter characteristics do not include g-cell frequency response.
MMA655x
Sensor
16
Freescale Semiconductor, Inc.
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